In recent years, a three-dimensional cross-point type nonvolatile memory device is proposed. This nonvolatile memory device includes a memory layer in which a plurality of memory cell array layers is stacked in a height direction. In the memory cell array layer, nonvolatile memory cells, in each of which a rectifying element and a nonvolatile memory element such as a variable resistive element are connected in series, are arranged to be sandwiched at intersection positions of a plurality of word lines and a plurality of bit lines formed at a height different from the word lines. Moreover, peripheral circuits such as a column control circuit that controls the bit lines of the memory cell array layer and performs access to a memory cell and a row control circuit that selects a word line of the memory cell array layer and applies a voltage needed for access to the memory cell are provided at a lower portion of the memory cell array layer above a semiconductor substrate. Therefore, the word lines and the bit lines drawn to a region out of a memory-cell forming region and the peripheral circuits are connected by word line contacts and bit line contacts that are provided to penetrate through the memory layer (for example, see Japanese Patent Application Laid-open No. 2009-130140).
As disclosed in Japanese Patent Application Laid-open No. 2009-130140, while the word line contact can be shared by a plurality of word lines formed at the same position in a plan view, the bit line contact is provided to all of bit lines provided in the memory layer. Therefore, in the three-dimensional cross-point type nonvolatile memory device, with the increase of word lines and bit lines, many word line contacts and bit line contacts are needed, so that a problem arises in that an area of a memory cell including the memory-cell forming region and a contact forming region in which the word line contacts and the bit line contacts are formed increases.